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  1 features applications description sn65hvd1176 SN75HVD1176 slls563d ? july 2003 ? revised december 2007 www.ti.com profibus rs-485 transceivers process automation optimized for profibus networks ? chemical production ? signaling rates up to 40 mbps ? brewing and distillation ? differential output exceeds 2.1 v ? paper mills (54 ? load) factory automation ? low bus capacitance of 10 pf (max) ? automobile production meets the requirements of tia/eia-485-a ? rolling, pressing, stamping machines esd protection exceeds 10 kv hbm ? networked sensors failsafe receiver for bus open, short, idle general rs-485 networks up to 160 transceivers on a bus ? motor/motion control low skew during output transitions and ? hvac and building automation networks driver enabling / disabling ? networked security stations common-mode rejection up to 50 mhz short-circuit current limit hot swap capable thermal shutdown protection these devices are half-duplex differential transceivers, with characteristics optimized for use in profibus (en 50170) applications. the driver output differential voltage exceeds the profibus requirements of 2.1 v with a 54 ? load. a signaling rate of up to 40 mbps allows technology growth to high data transfer speeds. the low bus capacitance provides low signal distortion. the sn65hvd1176 and SN75HVD1176 meet or exceed the requirements of ansi standard tia/eia-485-a (rs-485) for differential data transmission across twisted-pair networks. the driver outputs and receiver inputs are tied together to form a half-duplex bus port, with one-fifth unit load, allowing up to 160 nodes on a single bus. the receiver output stays at logic high when the bus lines are shorted, left open, or when no driver is active. the driver outputs are in high impedance when the supply voltage is below 2.5 v to prevent bus disturbance during power cycling or during live insertion to the bus. an internal current limit protects the transceiver bus pins in short-circuit fault conditions by limiting the output current to a constant value. thermal shutdown circuitry protects the device against damage due to excessive power dissipation caused by faulty loading and drive conditions. the SN75HVD1176 is characterized for operation at temperatures from 0 c to 70 c. the sn65hvd1176 is characterized for operation at temperatures from -40 c to 85 c. 1 please be aware that an important notice concerning availability, standard warranty, and use in critical applications of texas instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. production data information is current as of publication date. copyright ? 2003 ? 2007, texas instruments incorporated products conform to specifications per the terms of the texas instruments standard warranty. production processing does not necessarily include testing of all parameters. 12 3 4 87 6 5 r rede d vccb a gnd d package (top view) ab d dere r logic diagram (positive logic)
absolute maximum ratings recommended operating conditions sn65hvd1176 SN75HVD1176 slls563d ? july 2003 ? revised december 2007 these devices have limited built-in esd protection. the leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the mos gates. available options t a packaged devices (1) package marking (2) 0c to 70c SN75HVD1176d vn1176 -40 c to 85 c sn65hvd1176d vp1176 (1) the d package is available taped and reeled. add an r suffix to the device type (for example, sn65hvd1176dr). (2) for the most current package and ordering information, see the package option addendum located at the end of this datasheet or see the ti website at www.ti.com . over operating junction temperature range unless otherwise noted (1) sn65hvd1176 unit SN75HVD1176 v cc supply voltage (2) ? 0.5 to 7 v voltage at any bus i/o terminal ? 9 to 14 v voltage input, transient pulse, a and b, (through 100 ? , see figure 15 ) ? 40 to 40 v voltage input at any d, de or re terminal ? 0.5 to 7 v i o receiver output current ? 10 to 10 ma all pins 4 kv human body model, electrostatic discharge bus terminals and (hbm) (3) 10 kv gnd t j junction temperature 150 c (1) stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. all voltage values are with respect to the network ground terminal unless otherwise noted. (2) all voltage values, except differential i/o bus voltages, are with respect to network ground terminal.. (3) tested in accordance with jedec standard 22. test method a114-a.. min typ max unit v cc supply voltage 4.75 5 5.25 v voltage at either bus i/o terminal a, b ? 7 12 v v ih high-level input voltage 2 v cc v d, de, re v il low-level input voltage 0 0.8 v v il differential input voltage a with respect to b -12 12 v driver -70 70 ma i o output current receiver -8 8 ma sn65hvd1176 -40 130 ? t j junction temperature (1) SN75HVD1176 0 130 ? r l differential load resistance 54 ? 1/t u1 signaling rate 40 mbps (1) see the thermal characteristics table for more information on maintenance of this requirement. 2 submit documentation feedback copyright ? 2003 ? 2007, texas instruments incorporated product folder link(s): sn65hvd1176 SN75HVD1176 www.ti.com
electrical characteristics sn65hvd1176 SN75HVD1176 slls563d ? july 2003 ? revised december 2007 over recommended operating conditions (unless otherwise noted) parameter test conditions min typ (1) max unit driver v o open-circuit output voltage a or b, no load 0 v cc v rl = 54 ? see figure 1 2.1 2.9 v steady-state differential output voltage with common-mode loading, |v od(ss) | magnitude (v test from -7 v to 12 v) 2.1 2.7 v see figure 2 change in steady-state differential output |v od(ss) | see figure 1 and figure 6 ? 0.2 0 0.2 v voltage between logic states v oc(ss) steady-state common-mode output voltage 2 2.5 3 v change in steady-state common-mode output v oc(ss) see figure 5 ? 0.2 0 0.2 v voltage v oc(pp) peak-to-peak common-mode output voltage 0.5 v differential output voltage over and under v od(ring) r l = 54 ? , c l = 50 pf, see figure 6 10% v od(pp) shoot i i input current d, de -50 50 m a i o(off) output current with power off v cc 2.5 v see receiver line input i oz high impedance state output current de at 0 v i os(p) peak short-circuit output current v os = ? 7 v to 12 v -250 250 ma v os > 4 v, de at v cc , see 60 90 135 ma output driving low figure 8 i os(ss) steady-state short-circuit output current vos < 1 v, -135 -90 -60 ma output driving high c od differential output capacitance see receiver c id pf receiver positive-going differential input voltage v it(+) seefigure 9 v o = 2.4 v, i o = ? 8 ma ? 80 ? 20 mv threshold negative-going differential input voltage vit( ? ) v o = 0.4 v, i o = 8 ma -200 -120 mv threshold v hys hysteresis voltage (v it+ ? v it- ) 40 mv v oh high-level output voltage v id = 200 mv, i oh = ? 8 ma, see figure 9 4 4.6 v v ol low-level output voltage v id = ? 200 mv, i ol = 8 ma, see figure 9 0.2 0.4 v i a , i b v cc = 4.75 v to 5.25 v v i = - 7 v to 12 v, bus pin input current ? 160 200 m a i a(off) other input = 0 v v cc = 0 v i b(off) i i receiver enable input current re ? 50 50 m a i oz high-impedance - state output current re = v cc ? 1 1 m a r i input resistance 60 k ? test input signal is a 1.5 mhz sine wave with c id differential input capacitance amplitude 1 vpp, capacitance measured across a 7 10 pf and b c mr common mode rejection see figure 11 4 v (1) all typical values are at v cc = 5 v and 25 c. copyright ? 2003 ? 2007, texas instruments incorporated submit documentation feedback 3 product folder link(s): sn65hvd1176 SN75HVD1176 www.ti.com
switching characteristics sn65hvd1176 SN75HVD1176 slls563d ? july 2003 ? revised december 2007 over recommended operating conditions (unless otherwise noted) parameter test conditions min typ ( max unit 1) driver t plh propagation delay time low-level-to-high-level output 4 7 10 ns t phl propagation delay time high-level-to-low-level output 4 7 10 ns rl = 54 ? , c l = 50 pf, t sk(p) pulse skew | t plh ? t phl | 0 2 ns see figure 3 t r differential output rise time 2 3 7.5 ns t f differential output fall time 2 3 7.5 ns t t(mlh) , t t(mhl) output transition skew see figure 4 0.2 1 ns t p(azh) , t p(bzh) propagation delay time, high-impedance-to-active 10 20 ns t p(azl) , t p(bzl) output t p(ahz) , t p(bhz) propagation delay time, active-to- high-impedance 10 20 ns t p(alz) , t p(blz) output re at 0 v |t p(azl) ? t p(bzh) | enable skew time 0.55 1.5 ns r l = 110 ? , |t p(azh) ? t p(bzl) | c l = 50 pf |t p(alz) ? t p(bhz) | see figure 7 disable skew time 2.5 ns |t p(ahz) ? t p(blz) | t p(azh) , t p(bzh) propagation delay time, high-impedance-to-active 1 4 m s t p(azl) , t p(bzl) output (from sleep mode) re at 5 v t p(ahz) , t p(bhz) propagation delay time, active-output-to 30 50 ns t p(alz) , t p(blz) high-impedance (to sleep mode) time from application of short-circuit to current t (cfb) see figure 8 0.5 m s foldback time from application of short-circuit to thermal t (tsd) t a = 25 c, see figure 8 100 m s shutdown receiver t plh propagation delay time, low-to-high level output 20 25 ns t phl propagation delay time, high-to-low level output 20 25 ns t sk(p) pulse skew | t plh ? t phl | see figure 10 1 2 ns t r receiver output voltage rise time 2 4 ns t f receiver output voltage fall time 2 4 ns propagation delay time, high-impedance-to-high-level t pzh 20 ns output de at v cc , see figure 13 propagation delay time, high-level-to-high-impedance 20 t phz ns output propagation delay time, high-impedance-to-low-level t pzl 20 ns output de at v cc , see figure 14 propagation delay time, low-level-to-high-impedance 20 t plz ns output propagation delay time, high-impedance-to-high-level t pzh 1 4 m s output (standby to active) de at 0 v, see figure 12 propagation delay time, high-level-to-high-impedance t phz 13 20 ns output (active to standby) propagation delay time, high-impedance-to-low-level t pzl 2 4 m s output (standby to active) de at 0 v, see figure 12 propagation delay time, low-level-to-high-impedance t plz 13 20 ns output (active to standby) (1) all typical values are at v cc = 5 v and 25 c. 4 submit documentation feedback copyright ? 2003 ? 2007, texas instruments incorporated product folder link(s): sn65hvd1176 SN75HVD1176 www.ti.com
thermal characteristics (1) parameter measurement information sn65hvd1176 SN75HVD1176 slls563d ? july 2003 ? revised december 2007 table 1. supply current parameter test conditions min typ max unit driver and receiver, re at 0 v, de at v cc , all other inputs open, no load 4 6 ma driver only, re at v cc , de at v cc , all other inputs open, no load 3.8 6 ma supply i cc current (1) receiver only, re at 0 v, de at 0 v, all other inputs open, no load 3.6 6 ma standby only, re at v cc , de at 0 v, all other inputs open 0.2 5 m a (1) over recommended operating conditions over recommended operating conditions (unless otherwise noted) parameter test conditions min typ (2) max unit low-k board (4) , no air flow 208.3 c/w q ja junction-to-ambient thermal resistance (3) high-k board (5) , no air flow 128.7 c/w q jb junction-to-board thermal resistance high-k board 77.6 c/w q jc junction-to-case thermal resistance 43.9 c/w r l = 54 ? , c l = 50 pf, 0 v to 3 v, p d device power dissipation 15 mhz, 50% duty cycle square wave 277 318 mw input, driver and receiver enabled sn65hvd1176 ? 40 64 c low-k board, no air flow, p d = 318 mw SN75HVD1176 0 c t a ambient air temperature sn65hvd1176 ? 40 89 c high-k board, no air flow, p d = 318 mw SN75HVD1176 0 c t sd thermal shut down junction temperature 150 c (1) see application information section for an explanation of these parameters. (2) all typical values are with v cc = 5 v and t a = 25 c. (3) the intent of q ja specification is solely for a thermal performance comparison of one package to another in a standardized environment. this methodology is not meant to and will not predict the performance of a package in an application-specific environment. (4) jesd51-3, low effective thermal conductivity test board for leaded surface mount packages. (5) jesd51-7, high effective thermal conductivity test board for leaded surface mount packages. note: test load capacitance includes probe and jig capacitance (unless otherwise specified). signal generator characteristics: rise and fall time < 6 ns, pulse rate 100 khz, 50% duty cycle, z o = 50 ? (unless otherwise specified). figure 1. driver test circuit, v od and v oc without common-mode loading copyright ? 2003 ? 2007, texas instruments incorporated submit documentation feedback 5 product folder link(s): sn65hvd1176 SN75HVD1176 www.ti.com i i i o i o v od 50 pf 27 27 v oc 0 v or 3 v ab d
sn65hvd1176 SN75HVD1176 slls563d ? july 2003 ? revised december 2007 parameter measurement information (continued) figure 2. driver test circuit, v od with common-mode loading figure 3. driver switching test circuit and rise/fall time measurement figure 4. driver switching waveforms for propagation delay and output midpoint time measurements figure 5. driver v oc test circuit and waveforms 6 submit documentation feedback copyright ? 2003 ? 2007, texas instruments incorporated product folder link(s): sn65hvd1176 SN75HVD1176 www.ti.com v od 60 v test 0 v or 3 v 375 375 v test = ?7 v to 12 v ab d v od 50 r l = 54 c l = 50 pf signal generator 3 v0 v v od(h) v od(l) 90% 10% t r t f input output t plh t phl 1.5 v 1.5 v 50% 50% 50% 50% t t(mlh) t t(mhl) d a,b ab v oc 50 signal generator ab 27 27 50 pf d v a v b v oc v oc(pp) ?v oc(ss) 3.25 v 1.75 v
sn65hvd1176 SN75HVD1176 slls563d ? july 2003 ? revised december 2007 parameter measurement information (continued) (1) v od(ring) is measured at four points on the output waveform, corresponding to overshoot and undershoot from the v od(h) and v od(l) steady state values. figure 6. v od(ring) waveform and definitions figure 7. driver enable/disable test copyright ? 2003 ? 2007, texas instruments incorporated submit documentation feedback 7 product folder link(s): sn65hvd1176 SN75HVD1176 www.ti.com v od(pp) v od(ring) v od(ring) v od(ss) v od(ss) 0 v differential a) d at logic low b) d at logic high de a b t p(azl) t p(alz) t p(bzh) t p(bhz) ab c l = 50 pf r l = 110 0 v de d signal generator 50 c l = 50 pf r l = 110 v cc 0 v 50% 50% 1.5 v v ol +0.5 v v ol ?0.5 v de a b t p(azh) t p(ahz) t p(bzl) t p(blz) ab c l = 50 pf r l = 110 3 v de d signal generator 50 c l = 50 pf r l = 110 v cc 0 v 50% 50% 1.5 v v oh ?0.5 v v oh +0.5 v 1.5 v 3 v 3 v
sn65hvd1176 SN75HVD1176 slls563d ? july 2003 ? revised december 2007 parameter measurement information (continued) figure 8. driver short-circuit test circuit and waveforms (short circuit applied at time t = 0) figure 9. receiver dc parameter definitions figure 10. receiver switching test circuit and waveforms figure 11. receiver common-mode rejection test circuit 8 submit documentation feedback copyright ? 2003 ? 2007, texas instruments incorporated product folder link(s): sn65hvd1176 SN75HVD1176 www.ti.com 60 250 135 i os voltage source v os output current |ma| t (cfb) t (tsd) time d v id v a v b i o a b i b v o r i a v ic v a + v b 2 50 signal generator c l = 15 pf 50 signal generator a v id b r i o v o 50% 90% 10% 1.5 v0 v v oh v ol t plh t phl t r t f input b input a output 1.5 v v i = a sin 2 ft 1 mhz < f < 50 mhz 100 nf 2.2 k v offset = ?2 v to 7 v 50 50 470 nf re rde d scope v r 2.2 k v cc 100 nf gnd ab scope v r shall be greater than 2 v throughout this test.
sn65hvd1176 SN75HVD1176 slls563d ? july 2003 ? revised december 2007 parameter measurement information (continued) figure 12. receiver enable time from standby (driver disabled) figure 13. receiver enable test circuit and waveforms, data output high (driver active) copyright ? 2003 ? 2007, texas instruments incorporated submit documentation feedback 9 product folder link(s): sn65hvd1176 SN75HVD1176 www.ti.com input generator 50 v o re r ab 3 v 1.5 v t pzh(2) 1.5 v 3 v0 v v oh gnd v i v o 0 v or 1.5 v 1.5 v or 0 v c l = 15 pf 20% v i 1 k 1% ab s1 a at 1.5 v b at 0 v s1 to b t pzl(2) 1.5 v 3 v v ol v o a at 0 v b at 1.5 v s1 to a 50 signal generator re b a 54 c l = 15 pf r 1 k 0 v v cc v cc dde re r 1.5 v t pzh t phz 3 v0 v v oh v oh ?0.5 v gnd 1.5 v
device information sn65hvd1176 SN75HVD1176 slls563d ? july 2003 ? revised december 2007 parameter measurement information (continued) figure 14. receiver enable test circuit and waveforms, data output low (driver active) figure 15. test circuit and waveforms, transient over-voltage test table 2. driver function table (1) input enable outputs d de a b h h h l l h l h x l z z x open z z open h h l (1) h = high level, l = low level, x = don ? t care, z = high impedance (off) table 3. receiver function table (1) diffrential input enable output v id = (v a ? v b ) re r v id 0.02 v l h (1) h = high level, l = low level, x = don ? t care, z = high impedance (off), ? = indeterminate 10 submit documentation feedback copyright ? 2003 ? 2007, texas instruments incorporated product folder link(s): sn65hvd1176 SN75HVD1176 www.ti.com 1 k pulse generator, 15 m s duration, 1% duty cycle 100 v test 0 v 15 m s 1.5 ms ?v test
sn65hvd1176 SN75HVD1176 slls563d ? july 2003 ? revised december 2007 table 3. receiver function table (continued) diffrential input enable output v id = (v a ? v b ) re r ? 0.2 v < v id < ? 0.02 v l ? v id ? 0.2 v l l x h z x open z open circuit l h short circuit l h idle (terminated) bus l h equivalent input and output schematic diagrams copyright ? 2003 ? 2007, texas instruments incorporated submit documentation feedback 11 product folder link(s): sn65hvd1176 SN75HVD1176 www.ti.com 9 v 500 200 k input v cc d and re inputs 9 v 500 200 k input v cc de input 16 v 16 v 90 k 18 k input a input 16 v16 v input b input 16 v 16 v v cc a and b outputs 9 v v cc r output 5 output v cc v cc output 18 k 18 k 18 k 90 k
typical characteristics sn65hvd1176 SN75HVD1176 slls563d ? july 2003 ? revised december 2007 figure 16. figure 17. figure 18. figure 19. 12 submit documentation feedback copyright ? 2003 ? 2007, texas instruments incorporated product folder link(s): sn65hvd1176 SN75HVD1176 www.ti.com 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 0 20 40 60 80 v cc = 4.75 v v cc = 5 v v cc = 5.25 v differential output voltage vs load current v od ? differential output v oltage ? v i l ? load current ? ma 100 50 t a = 25 c 54 56 58 60 62 64 66 0 10 20 30 40 50 signaling rate ? mbps driver supply current vs signaling rate i dd ? driver supply current ? marms v cc = 5 v t a = 25 c r l = 56 , de and re at 5 v input 0 v to 3 v prbs see no tag 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 ?40 ?15 10 35 60 85 v cc = 4.75 v v cc = 5 v v cc = 5.25 v driver output t ransition skew ? ns driver output transition skew vs free-air temperature t a ? free-air temperature ? c r l = 54 , c l = 50 pf see no tag 2 2.25 2.5 2.75 3 3.25 3.5 3.75 4 ?40 ?15 10 35 60 85 v cc = 4.75 v v cc = 5.25 v v cc = 5 v driver rise, fall t ime ? ns driver rise, fall time vs free-air temperature t a ? free-air temperature ? c r l = 54 , c l = 50 pf see no tag
sn65hvd1176 SN75HVD1176 slls563d ? july 2003 ? revised december 2007 typical characteristics (continued) figure 20. copyright ? 2003 ? 2007, texas instruments incorporated submit documentation feedback 13 product folder link(s): sn65hvd1176 SN75HVD1176 www.ti.com 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 ?40 ?15 10 35 60 85 v cc = 4.75 v v cc = 5.25 v t a ? free-air temperature ? c driver enable skew ? ns driver enable skew vs free-air temperature r l = 110 , c l = 50 pf see no tag v cc = 5 v
application information thermal characteristics of ic packages sn65hvd1176 SN75HVD1176 slls563d ? july 2003 ? revised december 2007 q ja ( junction-to-ambient thermal resistance) is defined as the difference in junction temperature to ambient temperature divided by the operating power. q ja is not a constant and is a strong function of: pcb design (50% variation) altitude (20% variation) device power (5% variation) q ja can be used to compare the thermal performance of packages if the specific test conditions are defined and used. standardized testing includes specification of pcb construction, test chamber volume, sensor locations, and the thermal characteristics of holding fixtures. q ja is often misused when it is used to calculate junction temperatures for other installations. ti uses two test pcbs as defined by jedec specifications. the low-k board gives average in-use condition thermal performance, and it consists of a single copper trace layer 25 mm long and 2-oz thick. the high-k board gives best case in-use condition, and it consists of two 1-oz buried power planes with a single copper trace layer 25 mm long and 2-oz thick. a 4% to 50% difference in q ja can be measured between these two test cards q jc ( junction-to-case thermal resistance) is defined as difference in junction temperature to case divided by the operating power. it is measured by putting the mounted package up against a copper block cold plate to force heat to flow from die, through the mold compound into the copper block. q jc is a useful thermal characteristic when a heatsink is applied to package. it is not a useful characteristic to predict junction temperature because it provides pessimistic numbers if the case temperature is measured in a nonstandard system and junction temperatures are backed out. it can be used with q jb in 1-dimensional thermal simulation of a package system. q jb ( junction-to-board thermal resistance) is defined as the difference in the junction temperature and the pcb temperature at the center of the package (closest to the die) when the pcb is clamped in a cold-plate structure. q jb is only defined for the high-k test card. q jb provides an overall thermal resistance between the die and the pcb. it includes a bit of the pcb thermal resistance (especially for bga ? s with thermal balls) and can be used for simple 1-dimensional network analysis of package system (see figure 21 ). figure 21. thermal resistance 14 submit documentation feedback copyright ? 2003 ? 2007, texas instruments incorporated product folder link(s): sn65hvd1176 SN75HVD1176 www.ti.com surface node jc calculated/measured junction jb calculated/measured pc board ca calculated ambient node q q q
packaging information orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ball finish msl peak temp (3) sn65hvd1176d active soic d 8 75 green (rohs & no sb/br) cu nipdau level-1-260c-unlim sn65hvd1176dg4 active soic d 8 75 green (rohs & no sb/br) cu nipdau level-1-260c-unlim sn65hvd1176dr active soic d 8 2500 green (rohs & no sb/br) cu nipdau level-1-260c-unlim sn65hvd1176drg4 active soic d 8 2500 green (rohs & no sb/br) cu nipdau level-1-260c-unlim SN75HVD1176d active soic d 8 75 green (rohs & no sb/br) cu nipdau level-1-260c-unlim SN75HVD1176dg4 active soic d 8 75 green (rohs & no sb/br) cu nipdau level-1-260c-unlim SN75HVD1176dr active soic d 8 2500 green (rohs & no sb/br) cu nipdau level-1-260c-unlim SN75HVD1176drg4 active soic d 8 2500 green (rohs & no sb/br) cu nipdau level-1-260c-unlim (1) the marketing status values are defined as follows: active: product device recommended for new designs. lifebuy: ti has announced that the device will be discontinued, and a lifetime-buy period is in effect. nrnd: not recommended for new designs. device is in production to support existing customers, but ti does not recommend using this part in a new design. preview: device has been announced but is not in production. samples may or may not be available. obsolete: ti has discontinued the production of the device. (2) eco plan - the planned eco-friendly classification: pb-free (rohs), pb-free (rohs exempt), or green (rohs & no sb/br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. tbd: the pb-free/green conversion plan has not been defined. pb-free (rohs): ti's terms "lead-free" or "pb-free" mean semiconductor products that are compatible with the current rohs requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. where designed to be soldered at high temperatures, ti pb-free products are suitable for use in specified lead-free processes. pb-free (rohs exempt): this component has a rohs exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. the component is otherwise considered pb-free (rohs compatible) as defined above. green (rohs & no sb/br): ti defines "green" to mean pb-free (rohs compatible), and free of bromine (br) and antimony (sb) based flame retardants (br or sb do not exceed 0.1% by weight in homogeneous material) (3) msl, peak temp. -- the moisture sensitivity level rating according to the jedec industry standard classifications, and peak solder temperature. important information and disclaimer: the information provided on this page represents ti's knowledge and belief as of the date that it is provided. ti bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. efforts are underway to better integrate information from third parties. ti has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ti and ti suppliers consider certain information to be proprietary, and thus cas numbers and other limited information may not be available for release. in no event shall ti's liability arising out of such information exceed the total purchase price of the ti part(s) at issue in this document sold by ti to customer on an annual basis. package option addendum www.ti.com 28-nov-2007 addendum-page 1
tape and reel information *all dimensions are nominal device package type package drawing pins spq reel diameter (mm) reel width w1 (mm) a0 (mm) b0 (mm) k0 (mm) p1 (mm) w (mm) pin1 quadrant sn65hvd1176dr soic d 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 q1 SN75HVD1176dr soic d 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 q1 package materials information www.ti.com 19-mar-2008 pack materials-page 1
*all dimensions are nominal device package type package drawing pins spq length (mm) width (mm) height (mm) sn65hvd1176dr soic d 8 2500 340.5 338.1 20.6 SN75HVD1176dr soic d 8 2500 340.5 338.1 20.6 package materials information www.ti.com 19-mar-2008 pack materials-page 2

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